1. Technical Field
The present invention relates to a data processing system in general, and in particular to a data processing system having a memory hierarchy. Still more particularly, the present invention relates to a data processing system capable of managing a virtual memory processing scheme without any assistance from an operating system.
2. Description of the Related Art
A prior art memory hierarchy typically includes one or more levels of cache memories, a system memory (also referred to as a real memory), and a hard disk (also referred to as a physical memory) connected to a processor complex via an input/output channel converter. When there are multiple levels of cache memories, the first level cache memory, commonly known as the level one (L1) cache, has the fastest access time and the highest cost per bit. The remaining levels of cache memories, such as level two (L2) caches, level three (L3) caches, etc., have a relatively slower access time, but also a relatively lower cost per bit. It is quite common that each lower cache memory level has a progressively slower access time.
The system memory is typically used to hold the most often used portions of process address space for a data processing system that employs a virtual memory processing scheme. Other portions of process address space are stored on the hard disk and will be retrieved as needed. During the execution of a software application, the operating system translates virtual addresses to real addresses. With the assistance of a Page Frame Table (PFT) stored within the system memory, the translation occurs at the granularity of pages of storage. A processor cache usually includes a translation lookaside buffer (TLB) that acts as a cache for the most recently used PFT entries (PTEs).
When a data load, data store, or instruction fetch request is initiated, a virtual address of the data associated with the request is looked up in the TLB to find a PTE that contains the corresponding real address for the virtual address. If the PTE is found in the TLB, the data load, data store, or instruction fetch request is issued to the memory hierarchy with the corresponding real address. If the PTE is not found in the TLB, the PFT within the system memory is utilized to locate the corresponding PTE. The PTE is then reloaded into the TLB and the translation process restarts.
Because of space constraints, not all virtual addresses can be fit into the PFT within the system memory. If a virtual-to-real address translation cannot be found in the PFT, or if the translation is found but the data associated with that page is not resided in the system memory, a page fault will occur to interrupt the translation process so that the operating system can update the PFT for a new translation. Such an update involves the moving of the page to be replaced from the system memory to the hard disk, invalidating all copies of the replaced PTE in the TLBs of all processors, moving the page of data associated with the new translation from the hard disk to the system memory, updating the PFT, and restarting the translation process.
As mentioned above, the management of virtual memories is typically performed by the operating system, and the portion of the operating system that manages the PFT and the paging of data between the system memory and the hard disk is commonly called the Virtual Memory Manager (VMM). However, there are several problems associated with the virtual memories being managed by the operating system. For example, the VMM is usually ignorant of the hardware structure and hence the replacement polices dictated by the VMM are generally not very efficient. In addition, the VMM code is very complex and expensive to maintain across multiple hardware platforms or even a single hardware platform that has many different possible memory configurations. The present disclosure provides a solution to the above-mentioned problems.